Paper Daily

  • (NIPS 2017) Visual Reference Resolution using Attention Memory for Visual Dialog, Paul Hongsuch Seo
    • An associative attention memory storing s sequence of previous (attention, key) pairs
    • Retrieves the previous attention, taking into account recency, which is most relevant for the current Q
    • Resoning ability, maybe the best single model (trained by mle) presently
    • Other keywords, text as key, attention as value, aceess values according to key; Method is Attention over attention

Computer Network Notes

  • Classes (think in binary system)
    • CA: 1-126 ($2^{24}-2$)
    • CB: 128-191 ($2^{16}-2$)
    • CC: 192-223 ($2^8-2$)
  • DBA: Directed Broadcast Address (NID, HID 1s [])
  • NID: (NID, HID 0s [])

Types of casting

  • Unicast
  • Broadcast
    • Limited
      • |m| (Source Address)| (Destination Address)|
    • Directed
      • |m|||

Subnets, Subnet Mask, CIDR

  • subnetting disadvantage
    • reach the process complexly
  • The difference between in subnet and outside subnet;
  • Every subnet waste two IP addresses for the NID and DBA
    • 2 subnet: For CC: (128 - 2) x 2 = 252
    • 2 subnet: (
  • Subnet Mask: 32 bit
    • #1: #NID + #SID, #0: #HID
    • can find out NID
  • Variable lenght subnet masking (VLSM)
  • Classless Inter Domain Routing
    • (a.b.c.d/n) n: #NID
    • Rules of blocks
      • All IP addrees should be contiguous
      • $2^n$
      • Fast IP address in the block should be evenly divided by size of the block
  • Subnetting in CIDR

Operating System Notes

File System

cache memory

  • Cache - Paging (main memory) - Secondary Memory
    • Hit latency: the time to hit in the cache
    • Cache hit: a state in which data requested for processing by a component or application is found in the cache memory
    • Cache miss: not found
    • Miss latency: the time (in cycles) the CPU waits when a miss happen in the cache
    • Page fault, Page hit
    • Spatial/temporal locality
  • Direct Mapping
    • [Tag | Index (line number)| (block) Offset]
    • $2^m$ addresses
    • $2^k$ cache entries
    • $2^n$ block size
    • Step:
      • Use the index part of the address to find the appropriate cache entry
      • CHeck the tag to see if the entry contains the right data
      • If it does, then use the offset to the find the correct byte
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